Every time you ask a question in ChatGPT, your request triggers a data relay race. Information leaves memory, passes through a CPU for preprocessing, travels to a GPU for heavy calculations, and then returns — and the entire journey is repeated for every word the AI generates.
The bottleneck is structural — it means routing some of the most expensive and power-hungry chips in the industry for each request. This inefficiency is just that XCENAa startup with offices in South Korea and the US, is trying to solve. The four-year-old startup has designed a chip that puts computing capabilities much closer to DRAM — the fast, short-term memory chips that store data that the processor is actively using — allowing common data operations to be handled close to memory, without the costly round-trips between CPU, GPU and memory.
If it works at scale, the implications for AI infrastructure costs could be significant, which largely explains the investor excitement around the company. Indeed, XCENA just raised $135 million in a Series B at a $570 million valuation, bringing its total to $185 million.
XCENA CEO Jin Kim co-founded the startup in 2022 with CTO Dohun Kim and CPO Harry Juhyun Kim, veterans of Samsung and SK Hynix, the memory giants that supply chips that power Nvidia’s GPUs. “CPUs and GPUs have gotten smarter over the decades. Memory never did. XCENA wants to change that,” Jin Kim told TechCrunch. “The recent rise in memory prices and related stocks indicates a broader shift in AI infrastructure toward memory-centric architectures,” he added. (This month, the three companies that dominate the global memory chip market — Samsung, SK Hynix and Micron — each crossed a trillion-dollar valuation for the first time.)
XCENA is betting on the premise that “inference is not just a computational problem; it’s increasingly a memory-scale problem,” Kim said.
XCENA’s chip, the MX1, connects to the CPU via CXL (Compute Express Link) – essentially a dedicated express lane between the processor and memory – processing data before it has to leave the memory module. It brings computation to data, not the other way around. The company claims that what used to require 10 servers could potentially be run on just one.
“While GPUs excel at matrix multiplication—the heavy math behind AI model training—much of the data orchestration that surrounds it, including preprocessing, KV cache management (the system that stores the previous conversation frame so a model doesn’t have to process it again), and data caching, is still performed on a CPU. Our chip handles these tasks directly within the memory module itself.
Demand for memory solutions has picked up since the second half of last year, and the company believes the timing is working in its favor.
Talks with several global memory suppliers are in the early stages, although Kim declined to name them. The company’s ideal customers are hyperscalers who spend tens of billions a year on AI infrastructure, where even a small gain in memory performance can mean hundreds of millions in savings.
The MX1 is still a prototype. Mass-produced chips are scheduled to roll off Samsung’s foundry lines by the end of 2026, with the company expecting to generate revenue from 2027.
While neural processing unit (NPU) manufacturers compete to challenge Nvidia for training workloads, XCENA targets the memory-intensive layer that lies beneath it all.
XCENA’s closest rivals include Astera Labs and Marvell, Nasdaq-listed companies working on next-generation memory connectivity. Marvell is a large, established player already working in the same space, Kim said, adding that the difference is intellectual property. “We have thousands of cores,” Kim said. Based on the public specification, Marvell’s approach relies on a handful of general-purpose cores by comparison.
These cores are built on RISC-V – an open source chip design scheme – and optimized specifically for data processing, with each core intentionally kept small and efficient. Beyond the cores themselves, XCENA designs its own internal memory, bus interface and DRAM controller hierarchy — a level of vertical integration that most chip companies, including larger rivals, typically outsource.
Seoul-based VC firms Atinum and IMM Investment co-led the Series B round, along with Corstone Asia and existing investors SBI Investment and Mirae Asset Capital. The company, which has more than 90 employees in offices in Pangyo, a tech hub outside Seoul, and in Sunnyvale, is also in talks with international investors about additional funding.
When you purchase through links in our articles, we may earn a small commission. This does not affect our editorial independence.
